The present invention relates to semiconductor integrated circuit devices (or semiconductor devices), and more particularly to a technique effectively adaptable to a semiconductor integrated circuit device including a memory array unit.
Japanese Unexamined Patent Application Publication No. 2011-14731 (Patent Literature 1) concerns an embedded DRAM (Dynamic Random Access Memory), or eDRAM, in which a memory array unit is integrated in a logic chip. This publication discloses that, in a COB (Capacitor Over Bitline) memory array unit, an interlayer insulating film between layers in which a memory capacitor is provided is a low dielectric constant (Low-k) silicon oxide-based insulating film such as SiOC.
Japanese Unexamined Patent Application Publication No. 2011-114049 (Patent Literature 2) or US Patent Published Application No. 2011-121375 (Patent Literature 3) corresponding thereto discloses a COB embedded DRAM with a memory capacitor provided in the same layers with interconnection layers of a logic circuit unit (this capacitor is occasionally referred to as “interconnection-layer intrusion-type memory capacitor” in this application).
Japanese Unexamined Patent Application Publication No. 2011-142214 (Patent Literature 4) or US Patent No. 2011-165756 (Patent Literature 5) corresponding thereto discloses a guard ring that is formed in a COB embedded DRAM so as to surround a memory array and is made of mainly metal materials such as tungsten.